Miniaturization of consumer electronics with increased functionality and high density memory has long been one of the major drivers in semiconductor packaging developments. Extremely dense electronics can be created by stacking thin silicon chips with interconnections in the vertical direction. Through silicon via (TSV) process is one of the techniques used in the packaging industry which enables stacking of thin silicon integrated circuits (ICs) or dies to provide integration and a potential increase in the physical density of some electronic systems' functions. Additionally, this technology enables potential architectural configurations for 3-dimensional integration of multiple dies.
It is desirable to provide reliable packages with increased density.